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<div class="header">
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<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">Interrupt Masks<div class="ingroups"><a class="el" href="group__group__axidmac.html">AXIDMAC      (AXI Direct Memory Access Controller)</a><a class="el" href="group__group__axidmac.html">AXIDMAC      (AXI Direct Memory Access Controller)</a> &raquo;  &#124; <a class="el" href="group__group__axidmac__macros.html">Macros</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gaef2eb77a07970ffadd71f8fc61b287e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#gaef2eb77a07970ffadd71f8fc61b287e5">CY_AXIDMAC_INTR_COMPLETION</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_COMPLETION_Msk)</td></tr>
<tr class="memdesc:gaef2eb77a07970ffadd71f8fc61b287e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting.  <a href="#gaef2eb77a07970ffadd71f8fc61b287e5">More...</a><br /></td></tr>
<tr class="separator:gaef2eb77a07970ffadd71f8fc61b287e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacea2fcc746563a5ece8c58129f714cd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#gacea2fcc746563a5ece8c58129f714cd8">CY_AXIDMAC_INTR_SRC_BUS_ERROR</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_SRC_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:gacea2fcc746563a5ece8c58129f714cd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 1: Bus error for a load from the source.  <a href="#gacea2fcc746563a5ece8c58129f714cd8">More...</a><br /></td></tr>
<tr class="separator:gacea2fcc746563a5ece8c58129f714cd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3f062e0419b40f5de763044bbd89dcd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#gad3f062e0419b40f5de763044bbd89dcd">CY_AXIDMAC_INTR_DST_BUS_ERROR</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_DST_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:gad3f062e0419b40f5de763044bbd89dcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 2: Bus error for a store to the destination.  <a href="#gad3f062e0419b40f5de763044bbd89dcd">More...</a><br /></td></tr>
<tr class="separator:gad3f062e0419b40f5de763044bbd89dcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb76e42edeba6488fb09be47f21eee98"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#gadb76e42edeba6488fb09be47f21eee98">CY_AXIDMAC_INTR_INVALID_DESCR_TYPE</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_INVALID_DESCR_TYPE_Msk)</td></tr>
<tr class="memdesc:gadb76e42edeba6488fb09be47f21eee98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 3: Invalid descriptor type.  <a href="#gadb76e42edeba6488fb09be47f21eee98">More...</a><br /></td></tr>
<tr class="separator:gadb76e42edeba6488fb09be47f21eee98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54c70f8f06cc5b5d8cda554d8436f021"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#ga54c70f8f06cc5b5d8cda554d8436f021">CY_AXIDMAC_INTR_CURR_PTR_NULL</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_CURR_PTR_NULL_Msk)</td></tr>
<tr class="memdesc:ga54c70f8f06cc5b5d8cda554d8436f021"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 5: The channel is enabled and the current descriptor pointer is "0".  <a href="#ga54c70f8f06cc5b5d8cda554d8436f021">More...</a><br /></td></tr>
<tr class="separator:ga54c70f8f06cc5b5d8cda554d8436f021"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80dc737ee509a8ab60868056bb690f73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#ga80dc737ee509a8ab60868056bb690f73">CY_AXIDMAC_INTR_ACTIVE_CH_DISABLED</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk)</td></tr>
<tr class="memdesc:ga80dc737ee509a8ab60868056bb690f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 6: The channel is disabled and the data transfer engine is busy.  <a href="#ga80dc737ee509a8ab60868056bb690f73">More...</a><br /></td></tr>
<tr class="separator:ga80dc737ee509a8ab60868056bb690f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c2843060c5f933068ee3aef5a490c8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__axidmac__macros__interrupt__masks.html#ga1c2843060c5f933068ee3aef5a490c8e">CY_AXIDMAC_INTR_DESCR_BUS_ERROR</a>&#160;&#160;&#160;(AXI_DMAC_CH_INTR_DESCR_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:ga1c2843060c5f933068ee3aef5a490c8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 7: Bus error for a load of the descriptor.  <a href="#ga1c2843060c5f933068ee3aef5a490c8e">More...</a><br /></td></tr>
<tr class="separator:ga1c2843060c5f933068ee3aef5a490c8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gaef2eb77a07970ffadd71f8fc61b287e5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaef2eb77a07970ffadd71f8fc61b287e5">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_COMPLETION</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_COMPLETION&#160;&#160;&#160;(AXI_DMAC_CH_INTR_COMPLETION_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting. </p>

</div>
</div>
<a id="gacea2fcc746563a5ece8c58129f714cd8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacea2fcc746563a5ece8c58129f714cd8">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_SRC_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_SRC_BUS_ERROR&#160;&#160;&#160;(AXI_DMAC_CH_INTR_SRC_BUS_ERROR_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 1: Bus error for a load from the source. </p>

</div>
</div>
<a id="gad3f062e0419b40f5de763044bbd89dcd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad3f062e0419b40f5de763044bbd89dcd">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_DST_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_DST_BUS_ERROR&#160;&#160;&#160;(AXI_DMAC_CH_INTR_DST_BUS_ERROR_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 2: Bus error for a store to the destination. </p>

</div>
</div>
<a id="gadb76e42edeba6488fb09be47f21eee98"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadb76e42edeba6488fb09be47f21eee98">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_INVALID_DESCR_TYPE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_INVALID_DESCR_TYPE&#160;&#160;&#160;(AXI_DMAC_CH_INTR_INVALID_DESCR_TYPE_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 3: Invalid descriptor type. </p>

</div>
</div>
<a id="ga54c70f8f06cc5b5d8cda554d8436f021"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga54c70f8f06cc5b5d8cda554d8436f021">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_CURR_PTR_NULL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_CURR_PTR_NULL&#160;&#160;&#160;(AXI_DMAC_CH_INTR_CURR_PTR_NULL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 5: The channel is enabled and the current descriptor pointer is "0". </p>

</div>
</div>
<a id="ga80dc737ee509a8ab60868056bb690f73"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga80dc737ee509a8ab60868056bb690f73">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_ACTIVE_CH_DISABLED</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_ACTIVE_CH_DISABLED&#160;&#160;&#160;(AXI_DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 6: The channel is disabled and the data transfer engine is busy. </p>

</div>
</div>
<a id="ga1c2843060c5f933068ee3aef5a490c8e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1c2843060c5f933068ee3aef5a490c8e">&#9670;&nbsp;</a></span>CY_AXIDMAC_INTR_DESCR_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_AXIDMAC_INTR_DESCR_BUS_ERROR&#160;&#160;&#160;(AXI_DMAC_CH_INTR_DESCR_BUS_ERROR_Msk)</td>
        </tr>
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<p>Bit 7: Bus error for a load of the descriptor. </p>

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